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document no. e0223h30 (ver. 3.0) date published april 2002 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2001-2002 elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. data sheet 512mb unbuffered sdram s.o.dimm hb52rf649dc-b (64m words 72 bits, 2 bank) hb52rd649dc-b (64m words 72 bits, 2 bank) description the hb52rf649dc, hb52rd649dc are a 64m 72 2 banks synchronous dynamic ram small outline dual in-line memory module (s.o.dimm), mounted 18 pieces of 256m bits sdram sealed in tcp package and 1 piece of serial eeprom (2k bits) for presence detect (pd). an outline of the products is 144-pin zig zag dual tabs socket type compact and thin package. therefore, they make high density mounting possible without surface mount technology. they provide common data inputs and outputs. decoupling capacitors are mounted beside tcp on the module board. note: do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. features ? fully compatible with: jedec standard outline 8 bytes s.o.dimm ? 144-pin zig zag dual tabs socket type (dual lead out) ? pcb height: 33.02mm (1.30inch) ? lead pitch: 0.80mm ? 3.3v power supply ? clock frequency: 133mhz/100mhz (max.) ? lvttl interface ? data bus width: 72 ecc ? single pulsed /ras ? 4 banks can operates simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length (bl): 1, 2, 4, 8 ? 2 variations of burst sequence ? sequential ? interleave ? programmable /ce latency (cl): 2, 3 ? byte control by dqmb ? refresh cycles: 8192 refresh cycles/64ms ? 2 variations of refresh ? auto refresh ? self refresh ? low self refresh current : hb52rf649dc-xxbl (l-version) : hb52rd649dc-xxbl (l-version)
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 2 ordering information part number clock frequency mhz (max.) /ce latency package contact pad mounted devices hb52rf649dc-75b* 1 hb52rf649dc-75bl* 1 133 mhz 133 mhz 3 3 144-pin s.o.dimm gold 256m bits sdram tcp* 2 hb52rd649dc-a6b* 1 hb52rd649dc-a6bl* 1 100 mhz 100 mhz 2, 3 2, 3 notes: 1. 100mhz operation at /ce latency = 2. 2. please refer to the tsop products hm5225xx5b datasheet (e0082h) for detail information. pin configurations front side back side 2pin 60pin 62pin 144pin 1pin 59pin 61pin 143pin front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 73 nc 2 vss 74 ck1 3 dq0 75 vss 4 dq32 76 vss 5 dq1 77 cb2 6 dq33 78 cb6 7 dq2 79 cb3 8 dq34 80 cb7 9 dq3 81 vcc 10 dq35 82 vcc 11 vcc 83 dq16 12 vcc 84 dq48 13 dq4 85 dq17 14 dq36 86 dq49 15 dq5 87 dq18 16 dq37 88 dq50 17 dq6 89 dq19 18 dq38 90 dq51 19 dq7 91 vss 20 dq39 92 vss 21 vss 93 dq20 22 vss 94 dq52 23 dqmb0 95 dq21 24 dqmb4 96 dq53 25 dqmb1 97 dq22 26 dqmb5 98 dq54 27 vcc 99 dq23 28 vcc 100 dq55 29 a0 101 vcc 30 a3 102 vcc 31 a1 103 a6 32 a4 104 a7 33 a2 105 a8 34 a5 106 ba0 35 vss 107 vss 36 vss 108 vss
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 3 front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 37 dq8 109 a9 38 dq40 110 ba1 39 dq9 111 a10 (ap) 40 dq41 112 a11 41 dq10 113 vcc 42 dq42 114 vcc 43 dq11 115 dqmb2 44 dq43 116 dqmb6 45 vcc 117 dqmb3 46 vcc 118 dqmb7 47 dq12 119 vss 48 dq44 120 vss 49 dq13 121 dq24 50 dq45 122 dq56 51 dq14 123 dq25 52 dq46 124 dq57 53 dq15 125 dq26 54 dq47 126 dq58 55 vss 127 dq27 56 vss 128 dq59 57 cb0 129 vcc 58 cb4 130 vcc 59 cb1 131 dq28 60 cb5 132 dq60 61 ck0 133 dq29 62 cke0 134 dq61 63 vcc 135 dq30 64 vcc 136 dq62 65 /re 137 dq31 66 /ce 138 dq63 67 /w 139 vss 68 cke1 140 vss 69 /s0 141 sda 70 a12 142 scl 71 /s1 143 vcc 72 nc 144 vcc pin description pin name function a0 to a12 address input row address a0 to a12 column address a0 to a9 ba0, ba1 bank select address dq0 to dq63 data-input/output cb0 to cb7 check bit (data-input/output) /s0, /s1 chip select /re row address asserted bank enable /ce column address asserted /w write enable dqmb0 to dqmb7 byte input/output mask ck0, ck1 clock input cke0, cke1 clock enable sda data-input/output for serial pd scl clock input for serial pd vcc power supply vss ground nc no connection
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 4 serial pd matrix* 1 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 0 number of bytes used by module manufacturer 1 0 0 0 0 0 0 0 80 128 1 total spd memory size 0 0 0 0 1 0 0 0 08 256byte 2 memory type 0 0 0 0 0 1 0 0 04 sdram 3 number of row addresses bits 0 0 0 0 1 1 0 1 0d 13 4 number of column addresses bits 0 0 0 0 1 0 1 0 0a 10 5 number of banks 0 0 0 0 0 0 1 0 02 2 6 module data width 0 1 0 0 1 0 0 0 48 72 7 module data width (continued) 0 0 0 0 0 0 0 0 00 0 (+) 8 module interface signal levels 0 0 0 0 0 0 0 1 01 lvttl 9 sdram cycle time (highest /ce latency) (-75) 7.5ns 0 1 1 1 0 1 0 1 75 cl = 3 (-a6) 10ns 1 0 1 0 0 0 0 0 a0 10 sdram access from clock (highest /ce latency) (-75) 5.4ns 0 1 0 1 0 1 0 0 54 (-a6) 6ns 0 1 1 0 0 0 0 0 60 11 module configuration type 0 0 0 0 0 0 1 0 02 ecc 12 refresh rate/type 1 0 0 0 0 0 1 0 82 normal (7.8125s) self refresh 13 sdram width 0 0 0 0 1 0 0 0 08 8 14 error checking sdram width 0 0 0 0 1 0 0 0 08 8 15 sdram device attributes: minimum clock delay for back-to- back random column addresses 0 0 0 0 0 0 0 1 01 1 clk 16 sdram device attributes: burst lengths supported 0 0 0 0 1 1 1 1 0f 1, 2, 4, 8 17 sdram device attributes: number of banks on sdram device 0 0 0 0 0 1 0 0 04 4 18 sdram device attributes: /ce latency 0 0 0 0 0 1 1 0 06 2, 3 19 sdram device attributes: /s latency 0 0 0 0 0 0 0 1 01 0 20 sdram device attributes: /w latency 0 0 0 0 0 0 0 1 01 0 21 sdram module attributes 0 0 0 0 0 0 0 0 00 unbuffer 22 sdram device attributes: general 0 0 0 0 1 1 1 0 0e vcc 10% 23 sdram cycle time (2nd highest /ce latency) 10ns 1 0 1 0 0 0 0 0 a0 cl = 2 24 sdram access from clock (2nd highest /ce latency) 6ns 0 1 1 0 0 0 0 0 60 25 sdram cycle time (3rd highest /ce latency) undefined 0 0 0 0 0 0 0 0 00
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 5 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 26 sdram access from clock (3rd highest /ce latency) undefined 0 0 0 0 0 0 0 0 00 27 minimum row precharge time 0 0 0 1 0 1 0 0 14 20ns 28 row active to row active min (-75) 0 0 0 0 1 1 1 1 0f 15ns (-a6) 0 0 0 1 0 1 0 0 14 20ns 29 /re to /ce delay min 0 0 0 1 0 1 0 0 14 20ns 30 minimum /re pulse width (-75) 0 0 1 0 1 1 0 1 2d 45ns (-a6) 0 0 1 1 0 0 1 0 32 50ns 31 density of each bank on module 0 1 0 0 0 0 0 0 40 256m byte 32 address and command signal input setup time (-75) 0 0 0 1 0 1 0 1 15 1.5ns (-a6) 0 0 1 0 0 0 0 0 20 2.0ns 33 address and command signal input hold time (-75) 0 0 0 0 1 0 0 0 08 0.8ns (-a6) 0 0 0 1 0 0 0 0 10 1.0ns 34 data signal input setup time (-75) 0 0 0 1 0 1 0 1 15 1.5ns (-a6) 0 0 1 0 0 0 0 0 20 2.0ns 35 data signal input hold time (-75) 0 0 0 0 1 0 0 0 08 0.8ns (-a6) 0 0 0 1 0 0 0 0 10 1.0ns 36 to 61 superset information 0 0 0 0 0 0 0 0 00 future use 62 spd data revision code 0 0 0 1 0 0 1 0 12 rev. 1.2b 63 checksum for bytes 0 to 62 (-75) 0 1 0 1 1 1 0 1 5d 93 (-a6) 1 1 0 0 0 1 0 0 c4 196 64 manufacturer?s jedec id code 0 0 0 0 0 1 1 1 07 hitachi 65 to 71 manufacturer?s jedec id code 0 0 0 0 0 0 0 0 00 72 manufacturing location * 2 (ascii-8bit code) 73 manufacturer?s part number 0 1 0 0 1 0 0 0 48 h 74 manufacturer?s part number 0 1 0 0 0 0 1 0 42 b 75 manufacturer?s part number 0 0 1 1 0 1 0 1 35 5 76 manufacturer?s part number 0 0 1 1 0 0 1 0 32 2 77 manufacturer?s part number 0 1 0 1 0 0 1 0 52 r 78 manufacturer?s part number (-75) 0 1 0 0 0 1 1 0 46 f (-a6) 0 1 0 0 0 1 0 0 44 d 79 manufacturer?s part number 0 0 1 1 0 1 1 0 36 6 80 manufacturer?s part number 0 0 1 1 0 1 0 0 34 4 81 manufacturer?s part number 0 0 1 1 1 0 0 1 39 9 82 manufacturer?s part number 0 1 0 0 0 1 0 0 44 d 83 manufacturer?s part number 0 1 0 0 0 0 1 1 43 c 84 manufacturer?s part number 0 0 1 0 1 1 0 1 2d ?
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 6 byte no. function described bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hex value comments 85 manufacturer?s part number (-75) 0 0 1 1 0 1 1 1 37 7 (-a6) 0 1 0 0 0 0 0 1 41 a 86 manufacturer?s part number (-75) 0 0 1 1 0 1 0 1 35 5 (-a6) 0 0 1 1 0 1 1 0 36 6 87 manufacturer?s part number 0 1 0 0 0 0 1 0 42 b 88 manufacturer?s part number (-xxb) 0 0 1 0 0 0 0 0 20 (space) (-xxbl) 0 1 0 0 1 1 0 0 4c l 89 manufacturer?s part number 0 0 1 0 0 0 0 0 20 (space) 90 manufacturer?s part number 0 0 1 0 0 0 0 0 20 (space) 91 revision code 0 0 1 1 0 0 0 0 30 initial 92 revision code 0 0 1 0 0 0 0 0 20 (space) 93 manufacturing date year code (bcd) 94 manufacturing date week code (bcd) 95 to 98 assembly serial number * 3 99 to 125 m anufacturer specific data ? ? ? ? ? ? ? ? ? * 4 126 intel specification frequency 0 1 1 0 0 1 0 0 64 100mhz 127 intel specification /ce# latency support 1 1 0 0 1 1 1 1 cf cl = 2, 3 notes: 1. all serial pd data are not protected. 0: serial data, ?driven low?, 1: serial data, ?driven high?. these spd are based on rev.1.2b specification. 2. byte72 is manufacturing location code. (ex: in case of japan, byte72 is 4ah. 4ah shows ?j? on ascii code.) 3. bytes 95 through 98 are assembly serial number. 4. all bits of 99 through 125 are not defined (?1? or ?0?).
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 7 block diagram cke (d0 to d8) cke (d9 to d17) clk (d0, d1, d9,d10) vcc vcc (d0 to d17) vss vss (d0 to d17) c18 to c56 serial pd sda a0 a1 a2 vss scl u0 sda scl cke0 cke1 clk0 dqmb0 dq0 to dq7 8 n0, n1 d0 /s0 /s1 /re, /ce, /w a0 to a12, ba0, ba1 /cs dqm i/o0 to i/o7 dqmb1 dq8 to dq15 8 d1 /cs dqm i/o0 to i/o7 cb0 to cb7 8 n4, n5 d2 /cs dqm i/o0 to i/o7 dqmb2 dq16 to dq23 8 n6, n7 d3 /cs dqm i/o0 to i/o7 dqmb3 dq24 to dq31 8 a0 to a9, a11 to a12 ba0, /re, /ce, /w ra0 to ra9, ra11 to ra12 rba0, /rre, /rce, /rw n8, n9 d4 /cs dqm i/o0 to i/o7 d9 /cs dqm i/o0 to i/o7 d10 /cs dqm i/o0 to i/o7 d11 /cs dqm i/o0 to i/o7 d12 /cs dqm i/o0 to i/o7 d13 /cs dqm i/o0 to i/o7 dqmb4 dq32 to dq39 8 n10, n11 d5 /cs dqm i/o0 to i/o7 dqmb5 dq40 to dq47 8 n12, n13 d6 /cs dqm i/o0 to i/o7 dqmb6 dq48 to dq55 8 n14, n15 d7 /cs dqm i/o0 to i/o7 dqmb7 dq56 to dq63 8 n16, n17 d8 /cs dqm i/o0 to i/o7 d14 /cs dqm i/o0 to i/o7 d15 /cs dqm i/o0 to i/o7 d16 /cs dqm i/o0 to i/o7 d17 /cs dqm i/o0 to i/o7 * d0 to d7: 256m bits sdram tcp r0 to r1: 22 ? n0 to n17: network resistors (10 ? ) n18 to n21: network resistors (22 ? ) c0 to c17: 20pf c18 to c56: 0.1f u0: 2k bits eeprom clk (d3, d4, d12, d13) clk1 n2, n3 /re, /ce, /w a0 to a12, ba0, ba1 /rre, /rce, /rw ra0 to ra12, rba0, rba1 clk (d2, d5, d6, d11, d14, d15) clk (d7, d8, d16, d17) c0 to c15 vss a10, ba1 ra10, rba1 c16 to c17 vss n18 to n21 r0 to r1
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 8 electrical specifications absolute maximum ratings parameter symbol value unit note voltage on any pin relative to vss vt ?0.5 to vcc + 0.5 ( 4.6 (max.)) v 1 supply voltage relative to vss vcc ?0.5 to +4.6 v 1 short circuit output current iout 50 ma power dissipation pt 9.0 w operating temperature topr 0 to +65 c storage temperature tstg ?55 to +125 c note: 1. respect to vss. dc operating conditions (ta = 0 to +65c) parameter symbol min. max. unit note supply voltage vcc 3.0 3.6 v 1, 2 vss 0 0 v 3 input high voltage vih 2.0 vcc + 0.3 v 1, 4 input low voltage vil ?0.3 0.8 v 1, 5 ambient illuminance ? ? 100 lx notes: 1. all voltage referred to vss. 2. the supply voltage with all vcc pins must be on the same level. 3. the supply voltage with all vss pins must be on the same level. 4. vih (max.) = vcc + 2.0v for pulse width 3ns at vcc. 5. vil (min.) = vss ? 2.0v for pulse width 3ns at vss.
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 9 dc characteristics 1 (ta = 0 to 65c, vcc = 3.3v 0.3v, vss = 0v) parameter symbol grade max. unit test conditions notes operating current (cl = 2) icc1 -75 -a6 1260 1125 ma burst length = 1 trc = min. 1, 2, 3 (cl = 3) icc1 -75 -a6 1260 1125 ma standby current in power down icc2p 54 ma cke0 = vil, tck = 12ns 6 standby current in power down (input signal stable) icc2ps 36 ma cke0 = vil, tck = 7 standby current in non power down icc2n 360 ma cke0, /s = vih, tck = 12ns 4 active standby current in power down icc3p 72 ma cke0, /s = vih, tck = 12ns 1, 2, 6 active standby current in non power down icc3n 540 ma cke0, /s = vih, tck = 12ns 1, 2, 4 burst operating current (cl = 2) icc4 -75 -a6 1170 1170 ma tck = min., bl = 4 1, 2, 5 (cl = 3) icc4 -75 -a6 1485 1170 ma refresh current icc5 2250 ma trc = min. 3 self refresh current icc6 54 ma vih vcc ? 0.2v vil 0.2v 8 self refresh current (l-version) icc6 36 ma notes: 1. icc depends on output load condition when the device is selected. icc (max.) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, ck0/ck1 operating current. 7. after power down mode, no ck0/ck1 operating current. 8. after self refresh mode set, self refresh current. dc characteristics 2 (ta = 0 to 65c, vcc = 3.3v 0.3v, vss = 0v) parameter symbol grade min. max. unit test conditions notes input leakage current ili ?10 10 a 0 vin vcc output leakage current ilo ?10 10 a 0 vout vcc dq = disable output high voltage voh 2.4 ? v ioh = ?4 ma output low voltage vol ? 0.4 v iol = 4 ma
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 10 pin capacitance (ta = 25c, vcc = 3.3v 0.3v) parameter symbol pins max. unit notes input capacitance cin address 110 pf 1, 2, 4 input capacitance cin /re, /ce, /w, 110 pf 1, 2, 4 input capacitance cin /s0, /s1, ck0, ck1, cke0, cke1 65 pf 1, 2, 4 input capacitance cin dqmb 30 pf 1, 2, 4 input/output capacitance ci/o dq, cb 27 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1mhz, 1.4v bias, 200mv swing. 3. dqmb = vih to disable data-out. 4. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to 65c, vcc = 3.3v 0.3v, vss = 0v) -75 -a6 parameter symbol pc100 symbol min. max. min. max. unit notes system clock cycle time (cl = 2) tck tclk 10 ? 10 ? ns 1 (cl = 3) tck tclk 7.5 ? 10 ? ns ck high pulse width tckh tch 2.5 ? 3 ? ns 1 ck low pulse width tckl tcl 2.5 ? 3 ? ns 1 access time from ck (cl = 2) tac tac ? 6 ? 6 ns 1, 2 (cl = 3) tac tac ? 5.4 ? 6 ns data-out hold time toh toh 2.7 ? 3 ? ns 1, 2 ck to data-out low impedance tlz 2 ? 2 ? ns 1, 2, 3 ck to data-out high impedance thz ? 5.4 ? 6 ns 1, 4 input setup time tas, tcs, tds, tces tsi 1.5 ? 2 ? ns 1, 5 cke setup time for power down exit tcesp tpde 1.5 ? 2 ? ns 1 input hold time tah, tch, tdh, tceh thi 0.8 ? 1 ? ns 1 ref/active to ref/active command period trc trc 67.5 ? 70 ? ns 1 active to precharge command period tras tras 45 120000 50 120000 ns 1 active command to column command (same bank) trcd trcd 20 ? 20 ? ns 1 precharge to active command period trp trp 20 ? 20 ? ns 1 write recovery or data-in to precharge lead time tdpl tdpl 15 ? 20 ? ns 1 active (a) to active (b) command period trrd trrd 15 ? 20 ? ns 1 transition time (rise and fall) tt 1 5 1 5 ns refresh period tref ? 64 ? 64 ms
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 11 notes: 1. ac measurement assumes tt = 1ns. reference level for timing of input signals is 1.5v. 2. access time is measured at 1.5v. load condition is cl = 50pf. 3. tlz (min.) defines the time at which the outputs achieves the low impedance state. 4. thz (max.) defines the time at which the outputs achieves the high impedance state. 5. tces defines cke setup time to ck rising edge except power down exit command. test conditions ? input and output timing reference levels: 1.5v ? input waveform and output load: see following figures tt 2.4v 0.4v 0.8v 2.0v input t t i/o cl input waveform and output load
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 12 relationship between frequency and minimum latency parameter -75 -a6 frequency (mhz) 133 100 t ck (ns) symbol pc100 symbol 7.5 10 notes active command to column command (same bank) lrcd 3 2 1 active command to active command (same bank) lrc 9 7 = [lras+ lrp] 1 active command to precharge command (same bank) lras 6 5 1 precharge command to active command (same bank) lrp 3 2 1 write recovery or data-in to precharge command (same bank) ldpl tdpl 2 2 1 active command to active command (different bank) lrrd 2 2 1 self refresh exit time lsrex tsrx 1 1 2 last data in to active command (auto precharge, same bank) lapw tdal 5 4 = [ldpl + lrp] self refresh exit to command input lsec 9 7 = [lrc] 3 precharge command to high impedance (cl = 2) lhzp troh 2 2 (cl = 3) lhzp troh 3 3 last data out to active command (auto precharge, same bank) lapr 1 1 last data out to precharge (early precharge) (cl = 2) lep ?1 ?1 (cl = 3) lep ?2 ?2 column command to column command lccd tccd 1 1 write command to data in latency lwcd tdwd 0 0 dqmb to data in ldid tdqm 0 0 dqmb to data out ldod tdqz 2 2 cke to ck disable lcle tcke 1 1 register set to active command lrsa tmrd 1 1 /s to command disable lcdd 0 0 power down exit to command input lpec 1 1 notes: 1. lrcd to lrrd are recommended value. 2. be valid [desl] or [nop] at next command of self refresh exit. 3. except [desl] and [nop]
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 13 pin functions ck0, ck1 (input pin): ck is the master clock input to this pin. the other input signals are referred at ck rising edge. /s0, /s1 (input pin): when /s is low, the command input cycle becomes valid. when /s is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /re, /ce and /w (input pins): although these pin names are the same as those of conventional dram modules, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 to a12 (input pins): row address (ax0 to ax12) is determined by a0 to a12 level at the bank active command cycle ck rising edge. column address (ay0 to ay9) is determined by a0 to a9 level at the read or write command cycle ck rising edge. and this column address becomes burst access start address. a10 defines the precharge mode. when a10 = high at the precharge command cycle, both banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0, ba1(ba) is precharged. ba0, ba1 (input pin): ba0, ba1 is a bank select signal (ba). the memory array is divided into bank0, bank1, bank2 and bank3. if ba0 is low and ba1 is low, bank0 is selected. if ba0 is low and ba1 is high, bank1 is selected. if ba0 is high and ba1 is low, bank2 is selected. if ba0 is high and ba1 is high, bank3 is selected. cke0, cke1 (input pin): this pin determines whether or not the next ck is valid. if cke is high, the next ck rising edge is valid. if cke is low, the next ck rising edge is invalid. this pin is used for power-down mode, clock suspend mode and self refresh mode. dqmb0 to dqmb7 (input pins): read operation: if dqmb is high, the output buffer becomes high-z. if the dqmb is low, the output buffer becomes low-z (the latency of dqmb during reading is 2 clocks). write operation: if dqmb is high, the previous data is held (the new data is not written). if dqmb is low, the data is written (the latency of dqmb during writing is 0 clock). dq0 to dq63 (dq pins): data is input to and output from these pins. cb0 to cb7 (dq pins): data is input to and output from these pins. vcc (power supply pins): 3.3v is applied. vss (power supply pins): ground is connected. detailed operation part refer to the hm5225165b/hm5225805b/hm5225405b-75/a6/b6 datasheet.(e0082h)
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 14 physical outline 2 144 1.00 0.10 detail a 0.25 max 2.55 min 0.60 0.05 0.80 2-r2.00 3.70 23.20 4.60 2.10 32.80 4.00 0.10 3.80 max 1.50 0.10 4.00 0.10 (datum -a-) detail b r0.75 2.5 2.00 min 2r3.00 min 4.00 min 3.20 min 1 143 3.30 23.20 4.60 2.50 32.80 (datum -a-) 33.02 20.00 a b component area (front) unit: mm component area (back) (datum -a-) eca-ts2-0042-02 67.60
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 15 caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ics, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. in particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. mde0202 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
hb52rf649dc-b, hb52rd649dc-b data sheet e0223h30 (ver. 3.0) 16 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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